<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
		>
<channel>
	<title>Comments on: The Future of the Embedded Linux Market</title>
	<atom:link href="http://www.multicorepacketprocessing.com/the-future-of-the-embedded-linux-market/feed/" rel="self" type="application/rss+xml" />
	<link>http://www.multicorepacketprocessing.com/the-future-of-the-embedded-linux-market/</link>
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	<lastBuildDate>Fri, 14 Oct 2011 12:13:45 +0000</lastBuildDate>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=3.0.4</generator>
	<item>
		<title>By: Alex Bachmutsky</title>
		<link>http://www.multicorepacketprocessing.com/the-future-of-the-embedded-linux-market/comment-page-1/#comment-386</link>
		<dc:creator>Alex Bachmutsky</dc:creator>
		<pubDate>Tue, 22 Dec 2009 21:02:49 +0000</pubDate>
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		<description>Vincent,

I am not sure you are right.

For example, would Cavium be willing to provide a few years ago all their crypto additional instructions to the competition? Will Tilera be willing to provide to their competition the exact implementation of their distributed cache coherency mechanism? Would any vendor be willing to provide even the information about adding a particular hardware offload engines to their competition, less details on how it works?

Let us say that a vendor quadrupled their TLB size, will they be willing to give that fact out to their competition ahead of time? Etc, etc.

Chip vendors work on their next generation chip for very long time, and they definitely don&#039;t want for the competition to know about planned features, some of them deeply affecting Linux modules.
The only way I see it working is that chip vendors would work only on their proprietary distribution or a snapshot of a standard distribution, and will provide all the information only when the chip is out (and even that is the question mark). That would mean delay of software availability to board designers and system integrators.</description>
		<content:encoded><![CDATA[<p>Vincent,</p>
<p>I am not sure you are right.</p>
<p>For example, would Cavium be willing to provide a few years ago all their crypto additional instructions to the competition? Will Tilera be willing to provide to their competition the exact implementation of their distributed cache coherency mechanism? Would any vendor be willing to provide even the information about adding a particular hardware offload engines to their competition, less details on how it works?</p>
<p>Let us say that a vendor quadrupled their TLB size, will they be willing to give that fact out to their competition ahead of time? Etc, etc.</p>
<p>Chip vendors work on their next generation chip for very long time, and they definitely don&#8217;t want for the competition to know about planned features, some of them deeply affecting Linux modules.<br />
The only way I see it working is that chip vendors would work only on their proprietary distribution or a snapshot of a standard distribution, and will provide all the information only when the chip is out (and even that is the question mark). That would mean delay of software availability to board designers and system integrators.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Vincent JARDIN</title>
		<link>http://www.multicorepacketprocessing.com/the-future-of-the-embedded-linux-market/comment-page-1/#comment-385</link>
		<dc:creator>Vincent JARDIN</dc:creator>
		<pubDate>Tue, 22 Dec 2009 15:25:48 +0000</pubDate>
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		<description>Alex,

I do not believe a CPU vendor has to release all details of a chipset to a Linux distribution provider. What we are hoping from an ideal solution is that Linux vendors are providing a generic compilation and packaging solution which can be easily *customized* and cross compiled. Kernel and cross compilers should also be part of the combinations.

Right now, most embedded Linux distributions are not made of &quot;innovations&quot;. There is more innovation on Dekstop/Server Linux distributions (Redhat-Fedora-Mandriva-etc vs Ubuntu-Debian-etc): SPICE from Redhat, KVM with its userland management tools, GUIs, etc.

The embedded innovations are mainly from the CPU vendors (debuggers, gcc upgrades, Kernel optimizations, BSP optimizations, etc.).

Maybe, an ideal embedded solution from an embedded Linux vendor would mean:

  - to be able to use any toolchain, which is best optimized by the CPU vendors. So, typically for a same target, two tool chains would be useable with a same embedded Linux distribution: a default one from the Linux vendor and a CPU vendor one.
  - to be able to use any Linux kernel version within a range of kernels. It does not make sense to link a kernel version with a Linux distribution. For instance, most userland packages (apache for instance) can work with any Linux kernels. Some cannot work, but only for compilation issues! Once any Linux kernel can be used, some kernels can be from the CPU vendors with the most optimized BSPs and some kernels can be from the Linux vendors.
  - to provide profiling (oprofile, papi, etc.), coverage tools, debuggers that are closed to the CPU&#039;s capabilities.
  - to push forward Linux optimizations into the main Linux&#039;s git trees (RCU optimisations, system call latency, SMP locking, 32/64 bits ABIs with any combinations); it means to become a visible actor of key Open Source components (glibc, gcc, Kernel).</description>
		<content:encoded><![CDATA[<p>Alex,</p>
<p>I do not believe a CPU vendor has to release all details of a chipset to a Linux distribution provider. What we are hoping from an ideal solution is that Linux vendors are providing a generic compilation and packaging solution which can be easily *customized* and cross compiled. Kernel and cross compilers should also be part of the combinations.</p>
<p>Right now, most embedded Linux distributions are not made of &#8220;innovations&#8221;. There is more innovation on Dekstop/Server Linux distributions (Redhat-Fedora-Mandriva-etc vs Ubuntu-Debian-etc): SPICE from Redhat, KVM with its userland management tools, GUIs, etc.</p>
<p>The embedded innovations are mainly from the CPU vendors (debuggers, gcc upgrades, Kernel optimizations, BSP optimizations, etc.).</p>
<p>Maybe, an ideal embedded solution from an embedded Linux vendor would mean:</p>
<p>  &#8211; to be able to use any toolchain, which is best optimized by the CPU vendors. So, typically for a same target, two tool chains would be useable with a same embedded Linux distribution: a default one from the Linux vendor and a CPU vendor one.<br />
  &#8211; to be able to use any Linux kernel version within a range of kernels. It does not make sense to link a kernel version with a Linux distribution. For instance, most userland packages (apache for instance) can work with any Linux kernels. Some cannot work, but only for compilation issues! Once any Linux kernel can be used, some kernels can be from the CPU vendors with the most optimized BSPs and some kernels can be from the Linux vendors.<br />
  &#8211; to provide profiling (oprofile, papi, etc.), coverage tools, debuggers that are closed to the CPU&#8217;s capabilities.<br />
  &#8211; to push forward Linux optimizations into the main Linux&#8217;s git trees (RCU optimisations, system call latency, SMP locking, 32/64 bits ABIs with any combinations); it means to become a visible actor of key Open Source components (glibc, gcc, Kernel).</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Alex Bachmutsky</title>
		<link>http://www.multicorepacketprocessing.com/the-future-of-the-embedded-linux-market/comment-page-1/#comment-382</link>
		<dc:creator>Alex Bachmutsky</dc:creator>
		<pubDate>Mon, 21 Dec 2009 23:56:16 +0000</pubDate>
		<guid isPermaLink="false">http://www.multicorepacketprocessing.com/?p=602#comment-382</guid>
		<description>The problem is not only to support a particular multicore processor as an ISA, but to support in Linux the entire SoC with core interconnect, hardware offload engines, etc. This was the problem even before these acquisitions, and will become even bigger problem after. Let us assume the best case scenario when both Intel and Cavium continue to support other processor architectures. We still have two issues to be solved:

1) Will these two vendors provide full support for competing solutions with the same priority as their own, or the support for other processors will become a background task, running when there are extra cycles available from their own CPU support?
2) Will other vendors (for example, Freescale) provide their competitors Intel and Cavium with potentially sensitive information about their new upcoming processors?

My biggest concern would actually be the second question, because it requires strict internal firewall inside Intel and Cavium to make sure that there is no sensitive information transfer within their organizations.</description>
		<content:encoded><![CDATA[<p>The problem is not only to support a particular multicore processor as an ISA, but to support in Linux the entire SoC with core interconnect, hardware offload engines, etc. This was the problem even before these acquisitions, and will become even bigger problem after. Let us assume the best case scenario when both Intel and Cavium continue to support other processor architectures. We still have two issues to be solved:</p>
<p>1) Will these two vendors provide full support for competing solutions with the same priority as their own, or the support for other processors will become a background task, running when there are extra cycles available from their own CPU support?<br />
2) Will other vendors (for example, Freescale) provide their competitors Intel and Cavium with potentially sensitive information about their new upcoming processors?</p>
<p>My biggest concern would actually be the second question, because it requires strict internal firewall inside Intel and Cavium to make sure that there is no sensitive information transfer within their organizations.</p>
]]></content:encoded>
	</item>
</channel>
</rss>

